Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same

ABSTRACT

A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes first gate electrodes arranged a first distance apart from each other on a semiconductor substrate, second gate electrodes arranged a second distance, which is larger than the first distance, apart from each other on the semiconductor substrate, first diffusion layers formed in the semiconductor substrate, the first diffusion layers sandwiching the first gate electrodes, second diffusion layers formed in the semiconductor substrate, the second diffusion layers sandwiching the second gate electrodes, a first insulating film formed on the first diffusion layer, second insulating films formed on the side surfaces of the second gate electrodes, first silicide films formed on the first gate electrodes, second silicide films formed on the second gate electrodes, and third silicide films formed on the second diffusion layers.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Applications No. 2001-244557, filed Aug.10, 2001; and No. 2001-244558, filed Aug. 10, 2001, the entire contentsof both of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor memory deviceequipped with a memory transistor including a floating gate and acontrol gate and a peripheral transistor for controlling the memorytransistor, and to a method of manufacturing the particularsemiconductor memory device.

[0004] 2. Description of the Related Art

[0005] A NAND type flash memory, which is a kind of nonvolatile memory,comprises a memory transistor in which a floating gate and a controlgate are laminated one upon the other and a peripheral transistor isarranged to surround the periphery of the memory transistor. In manycases, the gate of the peripheral transistor is formed by using anelectrode material equal to that of the floating gate of the memorytransistor. The method of manufacturing the particular flash memory willnow be described briefly with reference to the accompanying drawings.

[0006]FIGS. 58A, 58B to 66A, 66B are cross sectional views collectivelyshowing a conventional method of manufacturing a semiconductor memorydevice. FIGS. 58A to 66A are cross sectional views perpendicular to theelement separating region included in the memory cell region. On theother hand, FIGS. 58B to 66B are cross sectional views perpendicular tothe gate electrode in the memory cell region.

[0007] In the first step, a first insulating film 12 forming a gateinsulating film is formed on a semi-conductor substrate (siliconsubstrate) 11, followed by forming a first electrode material layer 13on the first insulating layer 12, as shown in FIGS. 58A and 58B. Thefirst electrode material layer 13 is formed of a polycrystalline silicon(polysilicon) into which an impurity is not introduced. Then, a secondinsulating film 14 is formed on the first electrode material layer 13,followed by forming an element separating region of an STI (ShallowTrench Isolation) structure consisting of an element separatinginsulating film 15 such that the element separating insulating film 15extends through the second insulating film 14, the first electrodematerial layer 13, and the first insulating film 12 into thesemiconductor substrate 11.

[0008] In the next step, the element separating insulating film 15 ispartly etched such that the upper surface of the element separatinginsulating film 15 is positioned lower than the upper surface of thefirst electrode material layer 13, followed by peeling off the secondinsulating film 14, as shown in FIGS. 59A and 59B.

[0009] Then, a resist layer 16 a is formed on the first electrodematerial layer 13 in the PMOS region, as shown in FIGS. 60A and 60B.After formation of the resist layer 16 a, ion implantation using, forexample, phosphorus ions, is applied to the first electrode materiallayer 13 in the memory cell region with the resist layer 16 a used as amask, followed by applying anneal to the ion-implanted region so as toform N⁺-type first conductive layers 13 a, 13 b. Incidentally, thereference numeral 13 a shown in FIGS. 60A, 60B denotes the firstconductive layer in the memory cell region, and the reference numeral 13b shown in FIGS. 60A, 60B denotes the first conductive layer in the NMOSregion. It should also be noted that the first conductive layer 13 a inthe memory cell region performs the function of the floating gate of thememory transistor. After formation of the N⁺-type first conductivelayers 13 a, 13 b, the resist layer 16 a is removed.

[0010] In the next step, a resist layer 16 b is formed on the firstconductive layers 13 a, 13 b as shown in FIGS. 61A, 61B. After formationof the resist layer 16 b, ion implantation using, for example, boronions is applied to the first electrode material layer 13 in the PMOSregion, followed by applying annealing to the ion-implanted region so asto form a P⁺-type first conductive layer 13 c. After formation of theP⁺-first conductive layer 13 c, the resist layer 16 b is removed.

[0011] Then, a third insulating film 17 is deposited over the firstconductive layers 13 a, 13 b, 13 c and the element separating insulatingfilm 15, as shown in FIGS. 62A and 62B, followed by depositing a secondelectrode material layer 18 on the third insulating film 17. It shouldbe noted that the second electrode material layer 18 is formed ofpolysilicon into which an impurity is not introduced.

[0012] In the next step, a resist layer 19 is formed on the secondelectrode material layer 18, followed by patterning the resist layer 19,as shown in FIGS. 63A, 63B. The patterned resist layer 19 is used as amask in the next step for removing the second electrode material layer18, the insulating film 17 and the first conductive layers 13 a, 13 b,13 c, thereby forming the gate patterns of the memory transistor and theperipheral transistor. Then, the resist layer 19 is removed, followed bya post-oxidation treatment.

[0013] Then, an insulating film 22 is formed on the side surface of thegate of the peripheral transistor, as shown in FIGS. 64A, 64B, followedby forming a resist layer 23 on the first insulating film 12 and thesecond electrode material layer 18 included in the PMOS region. Theresist layer 23 thus formed is used as a mask in the subsequent step forintroducing, for example, arsenic (As) ions as an impurity by means ofion implantation, followed by diffusing the introduced impurity byannealing. As a result, a second conductive layer 18 a forming thecontrol gate of the memory transistor and N⁺-type source/drain diffusionlayers 21 are formed in the memory cell region. On the other hand, asecond conductive layer 18 b and N⁺-type source/drain diffusion layers24 are formed in the NMOS region. Then, the resist layer 23 is removed.

[0014] In the next step, a resist layer 25 is formed on the firstinsulating film 12 and the second conductive layers 18 a, 18 b in thememory cell region and the NMOS region. After formation of the resistlayer 25, ion implantation is performed by using, for example, boronions as an impurity, followed by applying annealing to the ion-implantedregion so as to diffuse the implanted boron ions. As a result, a secondconductive layer 18 c and P⁺-type source/drain layers 26 are formed inthe PMOS region. Then, the resist layer 25 is removed.

[0015] After removal of the resist layer 25, the first insulating layer12 is removed so as to expose the source/drain diffusion layers 21, 24and 26 to the outside, as shown in FIGS. 66A and 66B. Then, salicide(Self Aligned Silicide) films 27 a, 27 b, 27 c, 27 d consisting of ametal having a high melting point are formed on the second conductivelayers 18 a, 18 b, 18 c and the source/drain diffusion layers 21, 24,26, respectively. In this fashion, a memory transistor 28 is formed inthe memory cell region, and an NMOS transistor 29 and a PMOS transistor30 are formed in the peripheral circuit region.

[0016] In the memory cell region of the conventional semiconductormemory device described above, the salicide film 27 a is formed on thecontrol gate formed on the second conductive layer 18 a, and thesalicide film 27 d is also formed on the source/drain diffusion layer21.

[0017] However, if the salicide film 27 d is formed on the source/draindiffusion 21 of the memory cell region, it is possible for thereliability of the device characteristics such as the data retentioncharacteristics and the data program/erase endurance cyclecharacteristics to be reduced in the flash memory. Also, where thesalicide film 27 d is also formed on the source/drain diffusion layer 21of the memory cell region, a serious problem is brought about that thedegree of freedom in terms of the element design of the source-drain ofthe memory cell device is markedly limited in order to satisfy both theformation of the electrode material and the device operation.

[0018] It was customary to use CMOS transistors of a dual work functiongate in a nonvolatile memory for a low power consumption and in a highperformance transistor requiring a high operating speed. The CMOStransistors include a surface channel type NMOS transistor and a surfacechannel type PMOS transistor. For forming these transistors, anelectrode material into which an impurity is not introduced is depositedfirst. Then, arsenic (As) ions or phosphorus (P) ions, which are N-typeimpurities, are introduced by means of ion implantation into the gateregion of the NMOS transistor, and boron (B) ions, which are P-typeimpurities, are introduced by means of ion implantation into the gateregion of the PMOS transistor. What should be noted is that the gateelectrode of the dual work function gate structure was formed in thepast by separately implanting P-type and N-type impurities by lightexposure technology with the N-type gate electrode and the P-typeelectrode used as masks. However, the conventional method of forming agate electrode of the dual work function gate structure requires a largenumber of process steps and each process step is complex, leading to anincreased manufacturing cost of the semiconductor memory device.

BRIEF SUMMARY OF THE INVENTION

[0019] According to a first aspect of the present invention, there isprovided a semiconductor memory device provided with a memory cellregion having first gate electrodes and a peripheral circuit regionhaving second gate electrodes includes: first gate electrodes arranged afirst distance apart from each other on a semiconductor substrate;second gate electrodes arranged a second distance, which is larger thanthe first distance, apart from each other on the semiconductorsubstrate; first diffusion layers formed in the semiconductor substrate,the first diffusion layers sandwiching the first gate electrodes; seconddiffusion layers formed in the semiconductor substrate, the seconddiffusion layers sandwiching the second gate electrodes; a firstinsulating film formed on the first diffusion layer; second insulatingfilms formed on the side surfaces of the second gate electrodes; firstsilicide films formed on the first gate electrodes; second silicidefilms formed on the second gate electrodes; and third silicide filmsformed on the second diffusion layers.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0020]FIGS. 1A and 1B are cross sectional views collectively showing theconstruction of a semiconductor memory device according to a firstembodiment of the present invention;

[0021]FIGS. 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A,9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A and 14B are crosssectional views collectively showing the process of manufacturing asemiconductor memory device according to the first embodiment of thepresent invention;

[0022]FIGS. 15A and 15B are cross sectional views collectively showingthe construction of a semiconductor memory device according to a secondembodiment of the present invention;

[0023]FIGS. 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B,22A, 22B, 23A, 23B, 24A and 24B are cross sectional views collectivelyshowing the process of manufacturing a semiconductor memory deviceaccording to the second embodiment of the present invention;

[0024]FIGS. 25A, 25B, 26A, 26B, 27A, 27B, 28A, 28B, 29A, 29B, 30A, 30B,31A, 31B, 32A, 32B, 33A, 33B, 34A, 34B, 35A and 35B are cross sectionalviews collectively showing the process of manufacturing a semiconductormemory device according to a third embodiment of the present invention;

[0025]FIGS. 36A, 36B, 37A, 37B, 38A, 38B, 39A and 39B are crosssectional views collectively showing the process of manufacturing asemiconductor memory device according to a fourth embodiment of thepresent invention;

[0026]FIG. 40 is cross sectional view collectively showing theconstruction of a semiconductor memory device according to a fifthembodiment of the present invention;

[0027]FIG. 41 is cross sectional view collectively showing theconstruction of another semiconductor memory device according to thefifth embodiment of the present invention;

[0028]FIG. 42 is a cross sectional view showing the construction of asemiconductor memory device according to a sixth embodiment of thepresent invention in a direction perpendicular to the element separatingregion;

[0029]FIG. 43 is a cross sectional view showing the construction of asemiconductor memory device according to the sixth embodiment of thepresent invention in a direction perpendicular to the gate electrode;

[0030]FIGS. 44, 45, 46, 47, 48, 49, 50 and 51 are cross sectional viewscollectively showing the manufacturing process of a semiconductor memorydevice according to the sixth embodiment of the present invention;

[0031]FIG. 52 is a graph showing the I-V characteristics of thesemiconductor memory device according to the sixth embodiment of thepresent invention;

[0032]FIGS. 53, 54, 55, 56 and 57 are cross sectional views collectivelyshowing the manufacturing process of a semiconductor memory deviceaccording to a seventh embodiment of the present invention; and

[0033]FIGS. 58A, 58B, 59A, 59B, 60A, 60B, 61A, 61B, 62A, 62B, 63A, 63B,64A, 64B, 65A, 65B, 66A and 66B are cross sectional views collectivelyshowing the conventional manufacturing process of a semiconductor memorydevice.

DETAILED DESCRIPTION OF THE INVENTION

[0034] Some embodiments of the present invention will now be describedwith reference to the accompanying drawings.

[0035] [First Embodiment]

[0036] The first embodiment is directed to an example of theconstruction where a silicide film is not formed on the diffusion layerof the memory transistor, and all the insulating films between the firstand second conductive layers constituting the gates of the peripheraltransistor are removed. The first embodiment is directed to a NAND typeflash memory. However, it is possible to apply the technical idea of thepresent invention to other memories, e.g., a memory in which AND typememory cells are arranged to form a row, as far as the memory isconstructed such that a selecting gate is formed on one side or bothsides of the memory cell.

[0037]FIGS. 1A and 1B are cross sectional views collectively showing theconstruction of a semiconductor memory device according to a firstembodiment of the present invention. It should be noted that FIG. 1A isa cross sectional view perpendicular to the element separating region ofthe memory cell, and FIG. 1B is a cross sectional view perpendicular tothe gate electrode of the memory cell region.

[0038] As shown in FIGS. 1A and 1B, the semiconductor memory deviceaccording to the first embodiment of the present invention is providedwith a memory cell region and a peripheral circuit region consisting ofan NMOS region and a PMOS region. In the memory cell region, gates of amemory transistor 28 are formed a first distance X apart from eachother, and gates of an NMOS peripheral transistor 29 and a PMOSperipheral transistor 30 are formed a second distance Y, which is largerthan the first distance X, apart from each other. The gate of the memorytransistor 28 includes a first conductive layer 13 a forming a floatinggate and a second conductive layer 18 a forming a control gate. As shownin the drawing, an insulating film 17 is formed between the first andsecond conductive layers 13 a and 18 a. On the other hand, the gate ofthe peripheral transistor 29 includes a first conductive layer 13 b anda second conductive layer 18 b. Likewise, the gate of the peripheraltransistor 30 includes a first conductive layer 13 c and a secondconductive layer 18 c. It should be noted that an insulating film is notformed between the first conductive layer 13 b and the second conductivelayer 18 b. Also, an insulating film is not formed between the firstconductive layer 13 c and the second conductive layer 18 c. Theclearance between the gates of the memory transistor 28 is filled withan insulating film 22 a, and an insulating film 22 b is formed on eachof the side surfaces of the peripheral transistors 29 and 30. Theinsulating films 22 a and 22 b are formed simultaneously by the samematerial. First diffusion layers 21 are formed within the semiconductorsubstrate (silicon substrate) 11 in a manner to have the gate of thememory transistor 28 sandwiched therebetween. Also, second diffusionlayers 24 are formed within the semiconductor substrate 11 in a mannerto have the gate of the peripheral transistor 29 sandwichedtherebetween. Further, second diffusion layers 26 are formed within thesemiconductor substrate 11 in a manner to have the gate of theperipheral transistor 30 sandwiched therebetween. Salicide (Self AlignedSilicide) films 27 a, 27 b, and 27 c are formed on the gate of thememory transistor 28, on the gates of the peripheral transistors 29, 30,and on the second diffusion layers 24, 26. It should be noted that asalicide film is not formed on the diffusion layer 21 of the memorytransistor 28. The salicide films 27 a, 27 b, and 27 c are silicidefilms formed in self-aligned with a gate.

[0039] Incidentally, the clearance between the gates of the memorytransistor 28 is filled with the insulating film 22 a. However, it isnot absolutely necessary for the clearance noted above to be filledcompletely with the insulating film 22 a. It is possible for smallclearances such as voids to be present inside the insulating film 22 aas far as a salicide film is not formed on the diffusion layer 21. Also,FIG. 1A shows that the insulating film 22 a is deposited to reach thesurface of the gate of the memory transistor. However, it is notabsolutely necessary for the insulating film 22 a to be deposited toreach the surface of the gate of the memory transistor, as far as thesurface of the diffusion layer 21 is covered with the insulating film 22a. Further, it is possible for the gate of the memory transistor 28 andthe gate of the peripheral transistor 29 to be arranged, for example, asecond distance Y apart from each other.

[0040]FIGS. 2A, 2B to 14A, 14B are cross sectional views collectivelyshowing the manufacturing process of the semiconductor memory deviceaccording to the first embodiment of the present invention. Themanufacturing process of the semiconductor memory device according tothe first embodiment of the present invention will now be described withreference to FIGS. 2A, 2B to 14A, 14B.

[0041] In the first step, a first insulating film 12 forming a gateinsulating film is formed on a semiconductor substrate 11, as shown inFIGS. 2A and 2B. The first insulating film 12 has a thickness of, forexample, about 100 Å. Then, a first electrode material layer 13 isformed on the first insulating film 12. The first electrode materiallayer 13 consists of polysilicon into which an impurity is notintroduced. Then, a second insulating film 14 consisting of siliconnitride is formed on the first electrode material layer 13.Incidentally, an impurity is introduced into the channel region and thewell region by means of ion implantation before formation of the firstinsulating film 12 in order to control the channel regions of the memorytransistor and the peripheral transistor.

[0042] In the next step, the second insulating film 14, the firstelectrode material layer 13, the first insulating film 12 and thesemiconductor substrate 11 are selectively removed so as to form groovesfor element separation. An insulating film 15 for the elementseparation, which consists of, for example, a silicon oxide film, isdeposited within the groove for the element separation, followed byplanarizing the insulating film 15 for the element separation until thesurface of the second insulating film 14 is exposed to the outside. Inother words, the second insulating film 14 performs the function of astopper film in planarizing the insulating film 15 for the elementseparation. In this fashion, an element separating region of an STI(Shallow Trench Isolation) structure, which consists of the insulatingfilm 15 for the element separation, is formed.

[0043] After formation of the element separating region, the insulatingfilm 15 for the element separation is partly etched such that thesurface of the insulating film 15 for the element separation ispositioned lower than the surface of the first electrode material layer13, followed by peeling off the second insulating film 14, as shown inFIGS. 4A and 4B.

[0044] In the next step, a resist layer 16 is formed on the firstelectrode material layer 13, followed by patterning the resist layer 16such that the resist layer 16 is left unremoved on only the peripheralcircuit region. Then, ion implantation is applied to the first electrodematerial layer 13 in the memory cell region with the patterned resistlayer 16 used as a mask, followed by applying annealing to theion-implanted region of the first electrode material layer 13 so as toform a first conductive layer 13 a. Where the memory transistor isformed of an NMOS transistor, the ion implantation is performed byusing, for example, phosphorus (P) ions as an N-type impurity under thecondition that the first conductive layer 13 a has an impurityconcentration of, for example, about 2×10²⁰ cm⁻³. Incidentally, it isconceivable to use arsenic (As) as the N-type impurity in place of P.The first conductive layer 13 a formed as described above performs thefunction of the floating gate of the memory transistor. After formationof the first conductive layer 13 a, the resist layer 16 is removed.

[0045] In the next step, a third insulating film 17 consisting of, forexample, an ONO (Oxide Nitride Oxide) film is deposited to cover thefirst electrode material layer 13, the first conductive layer 13 a andthe insulating film 15 for the element separation, as shown in FIGS. 6A,6B. Then, the third insulating film 17 in the peripheral circuit regionis removed such that the third insulating film 17 is left unremoved inthe memory cell region alone.

[0046] Further, a second electrode material layer 18 is deposited on thethird insulating film 17, the first electrode material layer 13 and theinsulating film 15 for the element separation, as shown in FIGS. 7A and7B. It should be noted that the second electrode material layer 18 isformed of polysilicon into which an impurity is not introduced.

[0047] In the next step, a resist layer 19 is formed on the secondelectrode material layer 18, followed by patterning the resist layer 19,as shown in FIGS. 8A and 8B. Then, the first and second electrodematerial layers 13, 18, the first conductive layer 13 a and the thirdinsulating film 17 are removed with the patterned resist layer 19 usedas a mask, thereby forming the gate patterns of the memory transistorand the peripheral transistor.

[0048] In the next step, the resist layer 19 is removed as shown inFIGS. 9A and 9B. Then, a post-oxidation is performed so as to form anoxide film (not shown) on the gate. Further, a resist layer 20 is formedto cover the first insulating film 12 and the second electrode materiallayer 18, followed by patterning the resist layer 20 such that theresist layer 20 is left unremoved in the peripheral region alone, asshown in FIGS. 10A and 10B. Further, ion implantation is performed withthe patterned resist layer 20 used as a mask so as to form source/draindiffusion layers 21 within the semiconductor substrate 11 in the memorycell region. Where the memory transistor consists of an NMOS transistor,P or As is used as the impurity. Then, the resist layer 20 is removed.

[0049] In the next step, a fourth insulating film 22 is formed to coverthe first insulating film 12 and the second electrode material layer 18,as shown in FIGS. 11A and 11B. In this case, the fourth insulating film22 is formed to fill completely the clearance between the gates of thememory cell region and not to fill the clearance between the gates ofthe peripheral circuit region. In other words, the thickness A of thefourth insulating film 22 is determined to satisfy formula (1) givenbelow:

X/2≦A<Y/2  (1)

[0050] where X represents the distance between the gates of the memorycell region, Y represents the distance between the gates of theperipheral circuit region, and A represents the thickness of the fourthinsulating film 22.

[0051] For example, where the distance X between the gates of the memorycell region is set at F (minimum processing size) and the distance Ybetween the gates of the peripheral circuit region is set at 2F to 3F,the thickness A of the fourth insulating film 22 is set to satisfy therelationship of formula (2) given below:

[0052]F/2≦A<F to 3F/2  (2)

[0053] Incidentally, it is possible for the distance Y between the gatesof the peripheral circuit region to be 1.3 to 5.0 times as much as thedistance X between the gates of the memory cell region. In this case, itis possible for the gate of the selecting transistor to be included inthe gates of the peripheral circuit region.

[0054] Also, it is desirable for the fourth insulating film 22 to beformed of an oxide film. In other words, the fourth insulating film 22is formed of, for example, a TEOS (Tetra Ethyl Ortho Silicate) film, anozone TEOS film, an HTO (High Temperature Oxide) film, an SOG (spin OnGlass) film, a coating type oxide film, an SA-CVD (SemiAtmospheric—Chemical Vapor Deposition) film, a plasma CVD film, or a PSG(Phosphorus Silicate Glass) film.

[0055] In the next step, the fourth insulating film 22 is etched back soas to expose the surfaces of the second electrode material layer 18, thefirst insulating film 12 or the diffusion layer region of the peripheraltransistor, as shown in FIGS. 12A and 12B. As a result, a buriedinsulating film 22 a is formed in the clearance between the gates in thememory cell region, and a side wall insulating film 22 b is formed onthe side surface of each of the gates in the peripheral circuit region.

[0056] Further, a resist layer 23 is formed to cover the firstinsulating film 12 and the second electrode material layer 18, followedby patterning the resist layer 23 such that the resist layer 23 is leftunremoved in the PMOS region alone, as shown in FIGS. 13A and 13B. Then,ion implantation using, for example, arsenic (As) ions as an impurity isperformed with the patterned resist layer 23 used as a mask under theconditions that the accelerating energy is set at scores of KeV and thedose of the impurity is set at about 10¹⁵ cm⁻². In other words, animpurity is introduced into the second electrode material layer 18 inthe memory cell region, the second electrode material layer 18 in theNMOS region, and the semiconductor substrate 11. Then, the introducedimpurity is diffused by annealing so as to form a second conductivelayer 18 a in the memory cell region. Also, first and second conductivelayers 13 b, 18 b and N⁺-type source/drain diffusion layers 24 areformed in the NMOS region. It should be noted that the first conductivelayer 13 b of the NMOS region is formed by diffusing the impurityintroduced into the second electrode material layer 18 of the NMOSregion into the first electrode material layer 13 of the NMOS region.After formation of the first conductive layer 13 b, etc, referred toabove, the resist layer 23 is removed.

[0057] In the next step, a resist layer 25 is formed to cover the firstinsulating film 12 and the second electrode material layer 18, followedby patterning the resist layer 25 such that the resist layer 25 is leftunremoved in only the memory cell region and the NMOS region. Then, ionimplantation using, for example, boron (B) ions as an impurity isperformed with the patterned resist layer 25 used as a mask under theconditions that the accelerating energy is set at scores of KeV and thedose of the impurity is set at about 10¹⁵ cm⁻². In other words, animpurity is introduced into the second electrode material layer 18 inthe PMOS region and into the semiconductor substrate 11. Then, theintroduced impurity is diffused by annealing so as to form first andsecond conductive layers 13 c, 18 c and P⁺-type source/drain diffusionlayers 26 in the PMOS region. It should be noted that the firstconductive layer 13 c of the PMOS region is formed by diffusing theimpurity introduced into the second electrode material layer 18 of thePMOS region into the first electrode material layer 13 of the PMOSregion. After formation of the first and second conductive layers 13 c,18 c, etc., the resist layer 25 is removed.

[0058] In the next step, the oxide film on the gate is removed so as toexpose the surface of the gate to the outside and, at the same time, thefirst insulating film 12 is removed so as to expose the source/draindiffusion layers 24, 26 of the peripheral transistor to the outside, asshown in FIGS. 1A and 1B. Then, a film of a metal having a high meltingpoint such as Co (cobalt), Ti (titanium) or Ni (nickel) is deposited tocover the second conductive layers 18 a, 18 b, 18 c, the buriedinsulating film 22 a, the side wall insulating film 22 b and thesource/drain diffusion layers 24, 26, followed by applying annealing tothe film of the high melting point metal so as to carry out the reactionbetween the metal having a high melting point and silicon. As a result,the salicide films 27 a, 27 b, 27 c are formed on the second conductivelayer 18 a of the memory cell region, on the second conductive layers 18b, 18 c of the peripheral circuit region, and on the source/draindiffusion layers 24, 26, respectively. After formation of the salicidefilms 27 a, 27 b, 27 c, the unreacted film of the high melting pointmetal is removed. As a result, the memory transistor 28 in which asalicide film is not formed on the diffusion layer 21 is formed in thememory cell region, and the NMOS transistor 29 and the PMOS transistor30 in which the salicide films 27 c are formed on the diffusion layers24, 26 are formed in the peripheral circuit region.

[0059] Incidentally, after the element forming process described above,a known technology is employed for depositing an interlayer insulatingfilm (not shown) on the gate electrode, for forming a contact (notshown) consisting of, for example, tungsten (W) within the interlayerinsulating film, and for forming a wiring layer (not shown) connected tothe contact.

[0060] It is possible for the memory transistor 28 to be of P-type. Inthis case, an impurity is introduced into the first and second electrodematerial layers 13, 18 of the memory transistor 28 simultaneously withthe introduction of an impurity into the first and second electrodematerial layers 13, 18 of, for example, the PMOS transistor 30.

[0061] Also, it is possible for the diffusion layers 24, 26 of theperipheral transistors 29, 30 to be of an LDD (Lightly Doped Drain)structure or of a DDD (Double Diffused Drain) structure. To be morespecific, it suffices to form N⁻-type and P⁻-type diffusion layers inthe NMOS region and the PMOS region, respectively, in prescribed regionsof the semiconductor substrate 11 before deposition of the fourthinsulating layer 22, followed by forming the N⁺-type diffusion layer 24and the P⁺-type diffusion layer 26 as described above.

[0062] Also, since the surface of the semiconductor substrate 11 in thediffusion layer region of the peripheral transistor and the surface ofthe second electrode material layer 19 are exposed to the outside by theetching back of the fourth insulating film 22 in the process step shownin FIGS. 12A and 12B, it is possible to form a protective layer on eachof the surfaces of the semiconductor substrate 11 and the secondelectrode material layer 18 noted above. To be more specific, itsuffices to form a protective film by oxidizing each of these surfacesso as to form a thin oxide film or by depositing an oxide film on eachof these surfaces, followed by removing the protective film after theion implantation and activating step and before formation of thesalicide films 27 a, 27 b, 27 c shown in FIGS. 13A, 13B and 14A, 14B.

[0063] It is possible to omit the etch back step shown in FIGS. 12A and12B. In this case, after deposition of the fourth insulating film 22shown in FIGS. 11A and 11B, the ion implantation and activating stepshown in FIGS. 13A, 13B and 14A, 14B is carried out. In performing theion implantation treatment, it is necessary to control the acceleratingenergy such that the accelerated ions pass through the fourth insulatingfilm 22 deposited on the second electrode material layer 18 and on thefirst insulating film 12 so as to be implanted into the second electrodematerial layer 18 and into the semiconductor substrate 11.

[0064] According to the first embodiment of the present inventiondescribed above, the buried insulating film 22 a is formed in theclearance between the gates of the memory transistor, with the resultthat a salicide film is not formed on the diffusion layer 21 and thefloating gate of the memory transistor 28. As a result, thecharacteristics of the memory cell region as a flash memory are notaffected by the salicide film formation so as to make it possible toprevent the reliability in the device characteristics of the memorytransistor 28 from being lowered by the salicide film formation. Itshould also be noted that the salicide films 27 b, 27 c are formed onthe gate and on the diffusion layers 24, 26 in the peripheraltransistors 29, 30, respectively. It follows that it is possible tolower the resistance of the gate and the diffusion layers 24, 26 of theperipheral transistors 29, 30 and to lower the resistance of the controlgate of the memory transistor 28. It should be noted that the loweredresistance in each of the gate and the diffusion layers 24, 26 of theperipheral transistors 29, 30 controls the delay of the gate and theattenuation of the driving current so as to contribute to theimprovement in the performance of the circuit. Also, where the capacityof the memory cell array is increased, the lowered resistance in thecontrol gate of the memory transistor 28 permits controlling the voltagedrop caused by the resistance of the control gate. Also, since it ispossible to suppress the delay in the response time, the number ofdivisions of the array can be decreased so as to markedly contribute tothe miniaturization of the chip area. What should also be noted is thatthe controllability of the cell device can be improved by stabilizingthe voltage of the control gate.

[0065] It should also be noted that the salicide film 27 d is not formedon the source/drain diffusion layers 21 in the memory cell region. As aresult, even in the case where both the electrode material layerformation and the device operation are to be satisfied, it is possibleto avoid the problem that the degree of freedom in the element design ofthe memory cell is markedly limited.

[0066] Further, the separation of the first electrode layer 13 isself-aligned with the formation of the element separating region shownin FIGS. 3A, 3B so as to make it possible to miniaturize the cell size.

[0067] Still further, the first embodiment of the present inventionmakes it possible to manufacture a NAND type flash memory by employingthe salicide technology that is typically employed in many cases in themanufacture of a system LSI. In other words, the first embodiment of thepresent invention is highly effective for the manufacture of a mixedchip including a flash memory and a system LSI and requiring highperformance and high functionality of the element such as high speedoperability of the peripheral control circuit, low power consumption andlow driving voltage.

[0068] What should also be noted is that, since the salicide film 27 cis formed on the diffusion layers 24, 26 in the peripheral circuitregion, it is possible to decrease the resistance of the contactconnected to the diffusion layers 24, 26 without deteriorating thecharacteristics of the memory cell. It follows that it is possible tosuppress the reduction in the drive current of the peripheraltransistors 29, 30 that is caused by the voltage drop generated by thecontact resistance.

[0069] [Second Embodiment]

[0070] The second embodiment is directed to an example that aninsulating film having an open portion is formed in the clearancebetween the first and second conductive layers of the peripheraltransistor included in the semiconductor memory device according to thefirst embodiment of the present invention described above.

[0071]FIGS. 15A and 15B are cross sectional views collectively showingthe construction of a semiconductor memory device according to thesecond embodiment of the present invention. As shown in FIGS. 15A, 15B,the semiconductor memory device according to the second embodimentdiffers from the semiconductor memory device according to the firstembodiment in that, in the second embodiment, an insulating film 17having an open portion is formed between the first conductive layer 13 band the second conductive layer 18 b included in the peripheraltransistor 29 and between the first conductive layer 13 c and the secondconductive layer 18 c included in the peripheral transistor 30. Theinsulating film 17 is formed simultaneously with formation of theinsulating film 17 formed between the first conductive layer 13 a andthe second conductive layer 18 a included in the memory transistor 28.Also, the material of the insulating film 17 formed in each of theperipheral transistors 29, 30 is equal to that of the insulating film 17formed in the memory transistor 28. It is desirable for the open portion31 of the insulating film 17 to be arranged in the center between thefirst conductive layer 13 b and the second conductive layer 18 b and inthe center between the first conductive layer 13 c and the secondconductive layer 18 c. The open portions 31 of the insulating films 17are intended to permit the first conductive layers 13 b, 13 c to beelectrically connected to the second conductive layers 18 b, 18 c,respectively. Therefore, the number and shape of the open portions 31are not particularly limited as far as the first conductive layers 13 b,13 c are electrically connected to the second conductive layers 18 b, 18c, respectively. It is also possible to form a plurality of openportions 31 in the insulating film 17.

[0072]FIGS. 16A, 16B to 21A, 21B are cross sectional views collectivelyshowing the manufacturing process of the semiconductor memory deviceaccording to the second embodiment of the present invention. Themanufacturing method of the semiconductor memory device according to thesecond embodiment of the present invention will now be described withreference to FIGS. 16A, 16B to 21A, 21B. Incidentally, in describing themanufacturing process of the semiconductor memory device according tothe second embodiment of the present invention, the manufacturing stepssimilar to those in the manufacturing process of the semiconductormemory device according to the first embodiment will be describedbriefly such that an emphasis is placed on the manufacturing stepsdiffering from those in the manufacturing process of the semiconductormemory device according to the first embodiment of the presentinvention.

[0073] In the first step, a first conductive layer 13 a is formed in thememory cell region as in the first embodiment, as shown in FIGS. 2A, 2Bto SA, SB.

[0074] In the next step, a third insulating film 17 consisting of, forexample, an ONO film is deposited to cover the first electrode materiallayer 13, the first conductive layer 13 a and the insulating film 15 forthe element separation. Then, the third insulating film 17 in theperipheral circuit region is selectively removed so as to form the openportion 31.

[0075] After formation of the open portion 31, a second electrodematerial layer 18 is deposited so as to cover the third insulating film17, the first electrode material layer 13, the first conductive layer 13a and the insulating film 15 for the element separation, as shown inFIGS. 17A and 17B. Incidentally, the second electrode material layer 18is formed of polysilicon into which an impurity is not introduced.

[0076] In the next step, a resist layer 19 is formed on the secondelectrode material layer 18, followed by pattering the resist layer 19,as shown in FIGS. 18A and 18B. Then, the first and second electrodematerial layers 13, 18, the third insulating film 17 and the firstconductive layer 13 a are selectively removed by using the patternedresist layer 19 as a mask, thereby forming gate patterns of the memorytransistor and the peripheral transistors.

[0077] In the next step, the resist layer 19 is removed, followed by apost-oxidation so as to form an oxide film (not shown) on the gate, asshown in FIGS. 19A, 19B. Then, a resist layer 20 is formed to cover thefirst insulating film 12 and the second electrode material layer 18,followed by patterning the resist layer 20, as shown in FIGS. 20A and20B. Further, ion implantation is performed by using the patternedresist layer 20 as a mask so as to form N⁺-type source/drain diffusionlayers 21 in the memory cell region of the semiconductor substrate 11,followed by removing the resist layer 20.

[0078] After removal of the resist layer 20, a fourth insulating film 22is formed to cover the first insulating film 12 and the second electrodematerial layer 18 in a manner to satisfy the relationship given byformula (1) referred previously, as shown in FIGS. 21A and 21B.

[0079] In the next step, the fourth insulating film 22 is etched back soas to expose the surfaces of the second electrode material layer 18 andthe first insulating film 12 or the surfaces of the diffusion layerregions of the peripheral transistors, as shown in FIGS. 22A and 22B. Asa result, a buried insulating film 22 a is formed in the clearancebetween the gate electrodes in the memory cell region, and a side wallinsulating film 22 b is formed on the side surface of the gate electrodein the peripheral circuit region.

[0080] Then, a resist layer 23 is formed to cover the first insulatingfilm 12 and the second electrode material layer 18, followed bypatterning the resist layer 23, as shown in FIGS. 23A and 23B. Further,ion implantation is performed by using, for example, arsenic (As) ionsas an impurity, with the patterned resist layer 23 used as a mask,followed by applying annealing to the ion-implanted regions. As aresult, the introduced impurity is diffused so as to form a secondconductive layer 18 a in the memory cell region and to form the firstand second conductive layers 13 b, 18 b, and the N⁺-type source/draindiffusion layers 24 in the NMOS region. It should be noted that theimpurity introduced into the second electrode material layer 18 of theNMOS region is diffused through the open portion 31 of the thirdinsulating film 17 into the first electrode material 13 of the NMOSregion so as to form the first conductive layer 13 b in the NMOS region.Then, the resist layer 23 is removed.

[0081] After removal of the resist layer 23, a resist layer 25 is formedto cover the first insulating film 12 and the second electrode materiallayer 19, followed by patterning the resist layer 25, as shown in FIGS.24A and 24B. Then, ion implantation is performed by using, for example,boron (B) as an impurity, with the patterned resist layer 25 used as amask. The introduced impurity is diffused by annealing so as to form thefirst and second conductive layers 13 c, 18 c and the P⁺-typesource/drain diffusion layers 26 in the PMOS region. It should be notedthat the impurity introduced into the second electrode material layer 18of the PMOS region is diffused through the open portion 31 of the thirdinsulating film 17 into the first electrode material layer 13 of thePMOS region so as to form the first conductive layer 13 c of the PMOSregion. Then, the resist layer 25 is removed.

[0082] In the next step, the salicide films 27 a, 27 b, 27 c are formedto cover the second conductive layer 18 a in the memory cell region, thesecond conductive layers 18 b, 18 c in the peripheral circuit region,and the source/drain diffusion layers 24, 26 of the peripheral circuitregion, respectively, as shown in FIGS. 15A and 15B.

[0083] The second embodiment of the present invention described abovepermits producing effects similar to those produced by the firstembodiment described previously.

[0084] It should be noted that, in the second embodiment of the presentinvention, the third insulating films 17 each having the open portion 31are formed between the first conductive layer 13 b and the secondconductive layer 18 b in the peripheral transistor 29 and between thefirst conductive layer 13 c and the second conductive layer 18 c in theperipheral transistor 30. It follows that the edge portion of the gateelectrode in the NMOS region is of a three-layer structure including thefirst conductive layer 13 b, the second conductive layer 18 b and thethird insulating film 17 interposed between the first and secondconductive layers 13 b and 18 b. Likewise, the edge portion of the gateelectrode in the PMOS region is of a three-layer structure including thefirst conductive layer 13 c, the second conductive layer 18 c and thethird insulating film 17 interposed between the first and secondconductive layers 13 c and 18 c. On the other hand, the gate electrodein the memory cell transistor is of a three-layer structure includingthe first conductive layer 13 a, the second conductive layer 18 a andthe third insulating film 17 interposed between the first and secondconductive layers 13 a and 18 a. It follows that, concerning the edgeportion of the gate electrode to which is applied the gate processing,the peripheral transistors 29, 30 and the memory transistor 28 are equalto each other in the laminate structure of the gate. It follows that thegate processing can be applied simultaneously to the memory transistor28 and the peripheral transistors 29, 30 without changing the etchingconditions.

[0085] [Third Embodiment]

[0086] The third embodiment, which is equal in construction to thesecond embodiment described above, differs from the second embodiment inthat, in the third embodiment, the first electrode material in thememory transistor and the first electrode material in the peripheraltransistor, which is equal in the conductivity type to the memorytransistor, are rendered conductive simultaneously.

[0087]FIGS. 25A, 25B to 35A, 35B are cross sectional views collectivelyshowing the manufacturing process of a semiconductor memory deviceaccording to a third embodiment of the present invention. Themanufacturing method of the semiconductor memory device according to thethird embodiment of the present invention will now be described withreference to FIGS. 25A, 25B to 35A, 35B. In describing the manufacturingprocess of the semiconductor memory device according to the thirdembodiment of the present invention, the manufacturing steps equal tothose in the manufacturing process of the semiconductor memory deviceaccording to the first and second embodiments of the present inventionwill be omitted, and the manufacturing steps differing from those in thefirst and second embodiments will be described.

[0088] In the first step, a first electrode material layer 13 is formedon a first insulating film 12, followed by forming an insulating film 15for the element separation as shown in FIGS. 2A, 2B to 4A, 4B, as in thefirst embodiment.

[0089] In the next step, a resist layer 16 a is formed on the firstelectrode material layer 13, followed by patterning the resist layer 16a such that the resist layer 16 a is left unremoved on the PMOS regionalone, as shown in FIGS. 25A and 25B. Then, ion implantation isperformed for implanting impurity ions into the first electrode materiallayer 13 in the memory cell region and the NMOS region by using thepatterned resist layer 16 a as a mask, followed by applying annealing tothe first electrode material layer 13 so as to form first conductivelayers 13 a, 13 b. In this case, the ion implantation is carried out byusing, for example, phosphorus (P) as an impurity under the conditionsthat the accelerating energy is set at scores of KeV and the dose of theimpurity is set at about 10¹⁵ cm⁻². Incidentally, the reference numeral13 a shown in FIGS. 25A, 25B denotes the first conductive layer in thememory cell region, and the reference numeral 13 b shown in FIGS. 25A,25B denotes the first conductive layer in the NMOS region. Then, theresist layer 16 a is removed.

[0090] In the next step, a resist layer 16 b is formed to cover thefirst electrode material layer 13 and the first conductive layers 13 a,13 b, followed by patterning the resist layer 16 b such that the resistlayer 16 b is left unremoved on only the memory cell region and the NMOSregion. Then, impurity ions are introduced into the first electrodematerial layer 13 of the PMOS region by ion implantation with thepatterned resist layer 16 b used as a mask, followed by applyingannealing to the first electrode material layer 13 so as to form a firstconductive layer 13 c. In this ion implantation treatment, boron (B),for example, is used as a P-type impurity, and the ion implantation iscarried out under the conditions that the accelerating energy is set atscores of KeV and the dose of the impurity is set at about 10¹⁵ cm⁻².Then, the resist layer 16 b is removed.

[0091] After removal of the resist layer 16 b, a third insulating film17 consisting of, for example, an ONO film is deposited to cover thefirst conductive layers 13 a, 13 b, 13 c and the insulating film 15 forthe element separation, as shown in FIGS. 27A and 27B. Then, the thirdinsulating film 17 in the peripheral circuit region is selectivelyremoved so as to form an open portion 31.

[0092] In the next step, a second electrode material layer 18 isdeposited in a manner to cover the third insulating film 17, the firstconductive layers 13 b, 13 c and the insulating film 15 for the elementseparation, as shown in FIGS. 28A and 28B. The second electrode materiallayer 18 is formed of polysilicon into which an impurity is notintroduced.

[0093] Then, a resist layer 19 is formed on the second electrodematerial layer 18, followed by patterning the resist layer 18, as shownin FIGS. 29A, 29B. Further, the second electrode material layer 18, thethird insulating film 17 and the first conductive layers 13 a, 13 b, 13c are selectively removed by using the patterned resist layer 19 as amask, thereby forming gate patterns for the memory transistor and theperipheral transistors.

[0094] In the next step, the patterned resist layer 19 is removed asshown in FIGS. 30A and 30B, followed by applying a post-oxidation so asto form an oxide film (not shown) on the gate. Then, a resist layer 20is formed in a manner to cover the first insulating film 12 and thesecond electrode material layer 18, followed by patterning the resistlayer 20, as shown in FIGS. 31A and 31B. Further, ion implantation iscarried out by using the patterned resist layer 20 as a mask so as toform N⁺-type source/drain diffusion layers 21 in the semiconductorsubstrate 11 in the memory cell region, followed by removing thepatterned resist layer 20.

[0095] In the next step, a fourth insulating film 22 is formed to coverthe first insulating film 12 and the second electrode material layer 18in a manner to satisfy the relationship given by formula (1) referred topreviously. Then, the fourth insulating film 22 is etched back so as toexpose the surfaces of the second electrode material layer 18 and thefirst insulating film 12 or the surface of the diffusion layer region ofthe peripheral transistor to the outside, as shown in FIGS. 33A and 33B.As a result, a buried insulating film 22 a is formed in the clearancebetween the gate electrodes in the memory cell region, and a side wallinsulating film 22 b is formed on the side surface of the gate electrodein the peripheral circuit region.

[0096] In the next step, a resist layer 23 is formed to cover the firstinsulating film 12 and the second electrode material layer 18, followedby patterning the resist layer 23 such that the resist layer 23 is leftunremoved on the PMOS region, as shown in FIGS. 34A and 34B. Then, animpurity of, for example, arsenic (As) is introduced into the secondelectrode material layer 18 by means of ion implantation with thepatterned resist film 23 used as a mask, followed by applying annealingto the introduced impurity so as to diffuse the impurity. As a result, asecond conductive layer 18 a is formed in the memory cell region, and asecond conductive layer 18 b and N⁺-type source/drain diffusion layers24 are formed in the NMOS region. Then, the patterned resist layer 23 isremoved.

[0097] After removal of the patterned resist layer 23, a resist layer 25is formed to cover the first insulating film 12 and the second electrodematerial layer 18, followed by patterning the resist layer 25 such thatthe resist layer 25 is left unremoved on the memory cell region and theNMOS region, as shown in FIGS. 35A and 35B. Then, ion implantationusing, for example, boron (B) as an impurity is performed by using thepatterned resist layer 25 as a mask, followed by applying annealing tothe introduced impurity so as to diffuse the impurity. As a result, asecond conductive layer 18 c and P⁺-type source/drain diffusion layers26 are formed in the PMOS region. Then, the patterned resist layer 25 isremoved.

[0098] After removal of the patterned resist layer 25, the salicidefilms 27 a, 27 b, 27 c are formed on the second conductive layer 18 a inthe memory cell region, on the second conductive layers 18 b, 18 c inthe peripheral circuit region, and on the source/drain diffusion layers24, 26 in the peripheral circuit region, respectively, as in the secondembodiment described previously.

[0099] According to the third embodiment of the present inventiondescribed above, it is possible to obtain effects similar to thoseobtained in the first and second embodiments described previously.

[0100] Further, the first electrode material layers 13 in the memorytransistor 28 and the peripheral transistor 29 are simultaneouslyrendered conductive. It follows that the number of manufacturing processsteps can be decreased, and the semiconductor memory device can bemanufactured easily.

[0101] Incidentally, where the memory transistor 28 is of P-type, it isdesirable to render conductive the first electrode material layer 13 inthe memory cell region simultaneously in the step of renderingconductive the first electrode material layer 13 in the PMOS region.

[0102] [Fourth Embodiment]

[0103] The fourth embodiment, which is equal in construction to thethird embodiment described above, differs from the third embodiment inthat, in the fourth embodiment, a conductive material is used in formingfirst the first electrode material layer.

[0104]FIGS. 36A, 36B to 39A, 39B are cross sectional views collectivelyshowing the manufacturing process of a semiconductor memory deviceaccording to the fourth embodiment of the present invention. Themanufacturing method of the semiconductor memory device according to thefourth embodiment of the present invention will now be described withreference of FIGS. 36A, 36B to 39A, 39B. In describing the manufacturingprocess of the semiconductor memory device according to the fourthembodiment of the present invention, the manufacturing steps equal tothose in the manufacturing process of the semiconductor memory deviceaccording to the third embodiment of the present invention will beomitted, and the manufacturing steps differing from those in the thirdembodiment will be described.

[0105] In the first step, a first insulating film 12 forming a gateinsulating film is formed on a semiconductor substrate 11, as shown inFIGS. 36A and 36B. Then, an N⁺-type first conductive layer 41 into whichan impurity has been introduced is formed on the first insulating film12, followed by depositing a second insulating film 14 consisting ofsilicon nitride on the first conductive layer 41.

[0106] In the next step, the second insulating film 14, the firstconductive layer 41, the first insulating film 12 and the semiconductorsubstrate 11 are selectively removed so as to form a groove for theelement separation, as shown in FIGS. 37A and 37B. Then, an insulatingfilm 15 for the element separation consisting of a silicon oxide film isdeposited to fill the groove for the element separation, followed byplanarizing the insulating film 15 for the element separation until thesurface of the second insulating film 14 is exposed to the outside,thereby forming an element separating region of an STI structureconsisting of the insulating film 15 for the element separation.

[0107] In the next step, the element separation insulating film 15 ispartly etched so as to permit the surface of the element separatinginsulating film 15 to be positioned lower than the surface of the firstconductive layer 41, followed by peeling off the second insulating film14, as shown in FIGS. 38A and 38B. Then, a resist layer 16 is formed onthe first conductive layer 41, followed by patterning the resist layer16 such that the resist layer 16 is left unremoved on only the memorycell region and the NMOS region. Further, ion implantation is applied tothe first conductive layer 41 in the PMOS region with the patternedresist 16 used as a mask, followed by applying annealing so as to form aP⁺-type first conductive layer 42. In carrying out the ion implantation,boron (B), for example, is used as a P-type impurity, and the ionimplantation is carried out under the conditions that the acceleratingenergy is set at scores of KeV and the dose of the impurity is set atabout 10¹⁵ cm⁻². The dose of the impurity in the process step shown inFIGS. 39A, 39B is about twice as high as the dose of the impurity in thefirst conductive layer 41. Then, the patterned resist layer 16 isremoved.

[0108] Then, the process steps shown in FIGS. 27A, 27B to 35A, 35B arecarried out as in the third embodiment so as to manufacture asemiconductor memory device as shown in FIGS. 15A and 15B.

[0109] According to the fourth embodiment of the present inventiondescribed above, it is possible to obtain effects similar to thoseobtained in each of the first and second embodiments describedpreviously.

[0110] Further, it is possible to omit the process step for makingconductive the first electrode material layer 13 in the memory cellregion and the NMOS region. It follows that it is possible to decreasethe number of manufacturing process steps and to manufacture easily thesemiconductor memory device.

[0111] [Fifth Embodiment]

[0112] The fifth embodiment is directed to an example of a semiconductormemory device in which a selecting transistor controlling a memorytransistor is arranged in the vicinity of the memory transistor.

[0113]FIGS. 40A, 40B, 41A and 41B are cross sectional views each showingthe construction of a semiconductor memory device according to the fifthembodiment of the present invention. To be more specific, FIGS. 40A, 40Bshows the construction in the case where an insulating film is notformed in the clearance between the first and second conductive layersof the selecting transistor. On the other hand, FIGS. 41A, 41B shows theconstruction in the case where an insulating film having an open portionis formed in the clearance between the first and second conductivelayers of the selecting transistor. The semiconductor memory deviceaccording to the fifth embodiment will now be described with referenceto FIGS. 40A, 40B, 41A and 41B. Concerning the semiconductor memorydevice according to the fifth embodiment, the description of theconstruction similar to that of the semiconductor memory deviceaccording to any of the first to fourth embodiments described above isomitted and the differing construction alone will be described.

[0114] As shown in FIGS. 40A, 40B, 41A and 41B, a selecting transistoris arranged in the vicinity of the memory transistor in thesemiconductor memory device according to the fifth embodiment of thepresent invention. In each of the memory transistor and the selectingtransistor, an insulating film 22 a is formed between the adjacent gatesso as to cover the surface of a diffusion layer 21. Therefore, asalicide film 27 a is formed on each of the gates. However, a salicidefilm is not formed on the diffusion layer 21. Also, it is desirable forthe gate of the memory transistor and the gate of the selectingtransistor to be arranged apart from each other by the first distance Xreferred to previously.

[0115] According to the fifth embodiment, it is possible to obtaineffects similar to those obtained in each of the first and secondembodiments.

[0116] [Sixth Embodiment]

[0117] The sixth embodiment is directed to an example that, in forming aPMOS transistor comprising a P-type first conductive layer and an N-typesecond conductive layer, an electrode material into which an impurity isnot injected is used for forming the first conductive layer.

[0118]FIGS. 42 and 43 are cross sectional views collectively showing asemiconductor memory device according to the sixth embodiment of thepresent invention. Specifically, FIG. 42 is a cross sectional viewperpendicular to the element separating region of the memory cellregion. On the other hand, FIG. 43 is a cross sectional viewperpendicular to the gate electrode of the memory cell region.

[0119] As shown in FIG. 42, the semiconductor memory device according tothe sixth embodiment comprises a memory cell region and a peripheralcircuit region including an NMOS region and a PMOS region. A PMOStransistor 125 in the PMOS region includes P⁺-type first and secondconductive layers 113 c, 116 c formed on a semiconductor substrate 111,an insulating film 119 having an open portion 120 and formed on thesecond conductive layer 116 c, and an N⁺-type third conductive layer 121c formed on the insulating film 119 and the second conductive layer 116c. On the other hand, an NMOS transistor 124 in the NMOS region includesN⁺-type first and second conductive layers 113 b, 116 b formed on thesemiconductor substrate 111, an insulating film 119 having an openportion 120 and formed on the second conductive layer 116 b, and anN⁺-type third conductive layer 121 b formed on the insulating film 119and the second conductive layer 116 b. Further, a memory transistor 123in the memory region includes N⁺-type first and second conductive layers113 a, 116 a formed on the semiconductor substrate 111, an insulatingfilm 119 formed on the second conductive layer 116 a, and an N⁺-typethird conductive layer 121 a formed on the insulating film 119.

[0120] In the peripheral circuit region described above, it suffices forthe insulating film 119 to be present in only the edge portions betweenthe second conductive layer 116 b and the third conductive layer 121 band between the second conductive layer 116 c and the third conductivelayer 121 c. Therefore, it is desirable for the open portion 120 of theinsulating film 119 to be positioned in the centers between the secondconductive layer 116 b and the third conductive layer 121 b and betweenthe second conductive layer 116 c and the third conductive layer 121 c.Also, the open portion 120 of the insulating film 119 is intended topermit the first and second conductive layers 113 b, 116 b to beelectrically connected to the third conductive layer 121 b, and topermit the first and second conductive layers 113 c, 116 c to beelectrically connected to the third conductive layer 121 c. Therefore,the number of the open portions 120 and the shape of the open portion120 are not particularly limited as far as the first conductive layers113 b, 113 c and the second conductive layers 116 b, 116 b can beelectrically connected to the third conductive layers 121 b, 121 c,respectively. Also, it is possible to form a plurality of open portions120. Further, it is possible to remove all the insulating films 119 inthe peripheral circuit region.

[0121] In the memory cell region noted above, the first and secondconductive layers 113 a, 116 a perform the function of a floating gateof the memory transistor 123, and the third conductive layer 121 aperforms the function of a control gate of the memory transistor 123.

[0122] In general, a PMOS transistor includes a P-type conductive layer.However, the third conductive layer 121 c of the PMOS transistor 125according to the sixth embodiment of the present invention is formed ofan N⁺-type conductive layer. Therefore, in order to allow the thirdconductive layer 121 c to perform sufficiently the function of the gateof the PMOS transistor 125, it is desirable for each of the first tothird conductive layers 113 a, 113 b, 113 c, 116 a, 116 b, 116 c, 121 a,121 b and 121 b to have an impurity concentration not lower than 1×10¹⁸cm⁻³.

[0123] In the semiconductor memory device according to the sixthembodiment of the present invention, it is possible for the thirdconductive layers 121 b, 121 c in the NMOS region and the PMOS region tobe of the same conductivity type (N⁺), as shown in FIG. 42. Therefore,the third conductive layer 121 b of the NMOS transistor 124 need not beseparated from the third conductive layer 121 c of the PMOS transistor125 on the element separating insulating film 115. In other words, thethird conductive layer 121 b and the third conductive layer 121 c areformed contiguous on the element separating insulating film 115.

[0124] FIGS. 44 to 51 are cross sectional views collectively showing themanufacturing process of the semiconductor memory device according tothe sixth embodiment of the present invention. The manufacturing processof the semiconductor memory device according to the sixth embodimentwill now be described with reference to FIGS. 44 to 51.

[0125] In the first step, a first insulating film 112 forming a gateinsulating film is formed on a semiconductor substrate 111, followed byforming a first electrode material layer 113 on the first insulatingfilm 112, as shown in FIG. 44. The first electrode material layer 113 isformed of polysilicon into which an impurity is not introduced. Then, asecond insulating film 114 such as a silicon nitride film is depositedon the first electrode material layer 113.

[0126] In the next step, the second insulating film 114, the firstelectrode material layer 113, the first insulating film 112 and thesemiconductor substrate 111 are selectively removed so as to form agroove for the element separation, as shown in FIG. 45. Then, an elementseparating insulating film 115 such as an oxide film is deposited withinthe element separating groove, followed by planarizing the elementseparating insulating film 115 until the surface of the secondinsulating film 114 is exposed to the outside. In other words, thesecond insulating film 114 performs the function of a stopper film inplanarizing the element separating insulating film 115. As a result, anelement separating region of an STI (Shallow Trench Isolation) structureconsisting of the element separating insulating film 115 is formed.Then, the second insulating film 114 is peeled off.

[0127] In the next step, a second electrode material layer 116consisting of polysilicon into which an impurity is not injected isformed to cover the first electrode material layer 113 and the elementseparating insulating film 115, followed by removing the secondelectrode material layer 116 until the surface of the element separatinginsulating film 115 is exposed to the outside.

[0128] In the next step, a resist layer 117 is formed to cover thesecond electrode material layer 116 and the element separatinginsulating film 115, followed by patterning the resist layer 117 suchthat the resist layer 117 is left unremoved on the PMOS regions alone,as shown in FIG. 47. Then, ion implantation is applied to the secondelectrode material layer 116 in the memory cell region and the NMOSregion by using the patterned resist layer 117 as a mask. In this ionimplantation step, arsenic (As) or phosphorus (P) is used as an N-typeimpurity. Further, annealing is applied so as to allow the impurityimplanted into the second electrode material layer 116 to be diffusedinto the first electrode material layer 113, thereby forming N⁺-typefirst conductive layers 113 a, 113 b and second conductive layers 116 a,116 b. Then, the patterned resist layer 117 is removed.

[0129] After removal of the patterned resist layer 117, a resist layer118 is formed to cover the second conductive layers 116 a, 116 b and theelement separating insulating film 115, followed by patterning theresist layer 118 such that the patterned resist layer 118 is leftunremoved on only the memory cell region and the NMOS regions, as shownin FIG. 48. Then, ion implantation is applied to the second electrodematerial layer 116 in the PMOS region by using the patterned resistlayer 118 as a mask. In this ion implantation step, boron (B), forexample, is used as a P-type impurity. Then, annealing is applied so asto allow the impurity implanted into the second electrode material layer116 to be diffused into the first electrode material layer 113, therebyforming P⁺-type first conductive layer 113 c and second conductive layer116 c. Then, the patterned resist layer 118 is removed.

[0130] After removal of the patterned resist layer 118, a thirdinsulating film 119 is deposited to cover the second conductive layers116 a, 116 b, 116 c and the element separating insulating film 115, asshown in FIG. 49. Then, the third insulating film 119 in the peripheralcircuit region is partly removed so as to form an open portion 120, asshown in FIG. 50. Incidentally, it is possible to remove entirely thethird insulating film 119 in the peripheral circuit region in this step.However, it is desirable to form the open portion 120 so as to permitthe third insulating film 119 to remain in the peripheral circuitregion, too.

[0131] In the next step, a third insulating material layer 121 isdeposited to cover the third insulating film 119 and the secondconductive layers 116 b, 116 c, as shown in FIG. 51. It should be notedthat the third insulating material layer 121 is formed of polysiliconhaving an N-type impurity implanted thereinto. Then, a metal film 122consisting of, for example, tungsten silicide (WSi) is formed on thethird electrode material layer 121.

[0132] In the next step, the metal film 122 and the third electrodematerial layer 121 are selectively removed, as shown in FIGS. 42 and 43,thereby forming the gate patterns of the memory transistor 123 and theperipheral transistors 124, 125.

[0133]FIG. 52 is a graph showing the I-V characteristics of thesemiconductor memory device according to the sixth embodiment of thepresent invention in comparison with the prior art. In the graph of FIG.52, the I-V characteristics between the P⁺-gate consisting of the firstand second conductive layers 113 c, 116 c in the PMOS transistor 125 andthe N⁺-type gate consisting of the third conductive layer 121 c in thePMOS transistor 125 are evaluated. As a result, substantially linear I-Vcharacteristics, which is satisfactory, like the prior art, wereobtained as shown in FIG. 52. It follows that, even where the PMOStransistor 125 includes the P⁺-type gate and the N⁺-type gate as in thesixth embodiment, a PN junction is not formed so as to performsufficiently the function of the gate. What should be noted is that,according to the present invention, even a logic circuit having a powersource voltage not higher than 1.8 V can be driven directly withoutinternally boosting the CMOS circuit so as to make it possible to lowerthe power source voltage without increasing the number of circuitelements.

[0134] According to the sixth embodiment of the present invention, it ispossible to form the gate of the NMOS transistor 124 and the gate of thePMOS transistor 125 by using the third electrode material layers 121 ofthe same conductivity type. In other words, it is unnecessary to implantdifferent impurities by using the light exposure technology for formingthe gate of the NMOS transistor 124 and the gate of the PMOS transistor125. It follows that a CMOS transistor of the dual word function gatecan be manufactured easily.

[0135] Further, it is also possible to use the third electrode materiallayers 121 of the NMOS and PMOS transistor 124, 125 as a control gate ofthe memory transistor 123 without implanting different impurities so asto further facilitate the manufacturing process of the semiconductormemory device.

[0136] Also, it is possible to form the third conductive layer 121 b ofthe NMOS transistor 124 contiguous to the third conductive layer 121 cof the PMOS transistor 125 on the element separating insulating film115. As a result, it is unnecessary for the third conductive layer 121 band the third conductive layer 121 c to be positioned apart from eachother so as to make it possible to decrease the area occupied by theperipheral circuit region.

[0137] It should also be noted that, in the peripheral transistors 124,125, the third insulating film 119 having the open portion 120 is formedbetween the second conductive layer 116 b and the third conductive layer121 b and between the second conductive layer 116 c and the thirdconductive layer 121 c. Therefore, the edge portion of the gateelectrode is of a three-layer structure including the second conductivelayer 116 b, the third conductive layer 121 b and the third insulatingfilm 119 interposed between the second and third conductive layers 116 band 121 b, or of a three-layer structure including the second conductivelayer 116 c, the third conductive layer 121 c and the third insulatingfilm 119 interposed between the second and third conductive layers 116 cand 121 c. On the other hand, in the memory transistor 123, the gateelectrode is of a three-layer structure including the second conductivelayer 116 a, the third conductive layer 121 a, and the third insulatingfilm 119 interposed between the second and third conductive layers 116 aand 121 a over the entire regions of the second and third conductivelayers 116 a and 121 a. It follows that, concerning the edge portion ofthe gate electrode to which is applied the gate processing, the gates ofthe peripheral transistors 124, 125 and the memory transistor 123 havethe same laminate structure. It follows that the gate processing can beperformed simultaneously without changing the etching conditions for thememory transistor 123 and the peripheral transistors 124, 125.

[0138] It should also be noted that the first electrode material layer113 can be separated in a self-aligned fashion in forming the elementseparating region as shown in FIG. 45. It follows that the minimum cellsize that can be defined by the minimum size can be realized so as tomake it possible to miniaturize the cell size.

[0139] As described above, the present invention is highly effective fora system LSI (logic embedded memory) having a nonvolatile memory and alogic device of high performance peripheral circuit elements mountedtogether.

[0140] [Seventh Embodiment]

[0141] The seventh embodiment of the present invention is directed to anexample that, in forming the PMOS transistor including a P-type firstconductive layer and an N-type second conductive layer, an electrodematerial having an impurity introduced therein is used for forming thefirst conductive layer. Incidentally, the semiconductor memory deviceaccording to the seventh embodiment is equal in the final constructionto the semiconductor memory device according to the sixth embodiment.Therefore, the description on the construction of the semiconductormemory device is omitted.

[0142] FIGS. 53 to 57 are cross sectional views collectively showing themanufacturing process of the semiconductor memory device according tothe seventh embodiment of the present invention. The manufacturingprocess of the semiconductor memory device according to the seventhembodiment will now be described with reference to FIGS. 53 to 57.Incidentally, in describing the manufacturing process of thesemiconductor memory device according to the seventh embodiment, theprocess steps equal to those of the manufacturing process of thesemiconductor memory device according to the sixth embodiment will bedescribed briefly, and the differing process steps alone will bedescribed in detail.

[0143] In the first step, a first insulating film 112 forming a gateinsulating film is formed on a semiconductor substrate 111, followed byforming a first electrode material layer 131 on the first insulatingfilm 112, as shown in FIG. 53. The first electrode material layer 131 isformed of polysilicon having an N-type impurity such as phosphorus (P)or arsenic (As) introduced therein. Then, a second insulating film 114consisting of, for example, a silicon nitride film is deposited on thefirst electrode material layer 131.

[0144] In the next step, the second insulating film 114, the firstelectrode material layer 131, the first insulating film 112 and thesemiconductor substrate 111 are selectively removed so as to formgrooves for the element separation, as shown in FIG. 54. Then, anelement separating insulating film 115 consisting of, for example, anoxide film is formed to fill the grooves for the element separation,followed by planarizing the element separating insulating film 115 untilthe surface of the second insulating film 114 is exposed to the outside,thereby forming an element separating region of an STI structureconsisting of the element separating insulating film 115. Further, thesecond insulating film 114 is peeled off.

[0145] After the peeling of the second insulating film 114, a secondelectrode material layer 116 consisting of polysilicon into which animpurity is not introduced is formed to cover the first electrodematerial layer 131 and the element separating insulating film 115, asshown in FIG. 55, followed by removing the second electrode materiallayer 116 until the surface of the element separating insulating film115 is exposed to the outside.

[0146] In the next step, a resist layer 117 is formed to cover thesecond electrode material layer 116 and the element separatinginsulating film 115, followed by patterning the resist layer 117 suchthat the resist layer 117 is left unremoved on the PMOS region alone, asshown in FIG. 56. Then, annealing is applied by using the patternedresist layer 117 as a mask, thereby allowing the impurity contained inthe first electrode material layer 131 to be diffused into the secondelectrode material layer so as to form N⁺-type first conductive layers131 a, 131 b and second conductive layers 116 a, 116 b. Further, thepatterned resist layer 117 is removed.

[0147] After removal of the patterned resist layer 117, a resist layer118 is formed to cover the second conductive layers 116 a, 116 b and theelement separating insulating film 115, followed by patterning theresist layer 118 such that the resist layer 118 is left unremoved on thememory cell region and the NMOS region, as shown in FIG. 57. Then, ionimplantation is applied to the second electrode material layer 116 inthe PMOS region by using the patterned resist layer 118 as a mask. Theion implantation is performed by using, for example, boron (B) as aP-type impurity. Further, annealing is applied so as to permit theimpurity implanted into the second electrode material layer 116 to bediffused into the first electrode material layer 131, thereby formingP⁺-type first conductive layer 131 c and second conductive layer 116 c.Then, the patterned resist layer 118 is removed.

[0148] Further, the process steps shown in FIGS. 48 to 51 are applied asin the sixth embodiment so as to obtain a semiconductor memory deviceconstructed as shown in FIGS. 42 and 43.

[0149] According to the seventh embodiment of the present inventiondescribed above, it is possible to obtain effects similar to thoseobtained in the sixth embodiment. Further, it is possible to omit thestep of implanting an impurity into the first electrode material layers113 in the memory cell region and the MOS region.

[0150] Incidentally, it is possible to use polysilicon into which animpurity is not implanted for forming the first electrode material layer131 and to use polysilicon having an impurity implanted thereinto forforming the second electrode material layer 116. In this case, annealingis applied so as to diffuse the impurity contained in the secondelectrode material layer 116 into the first electrode material layer131, thereby forming the first and second conductive layers 131 a, 131b, 131 c, 116 a, 116 b and 116 c.

[0151] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the present invention in itsbroader aspects is not limited to the specific details andrepresentative embodiments shown and described herein. Accordingly,various modifications may be made without departing from the spirit orscope of the general inventive concept as defined by the appended claimsand their equivalents.

What is claimed is:
 1. A semiconductor memory device provided with amemory cell region having first gate electrodes and a peripheral circuitregion having second gate electrodes, comprising: said first gateelectrodes arranged a first distance apart from each other on asemiconductor substrate; said second gate electrodes arranged a seconddistance, which is larger than said first distance, apart from eachother on the semiconductor substrate; first diffusion layers formed inthe semiconductor substrate, said first diffusion layers sandwichingsaid first gate electrodes; second diffusion layers formed in thesemiconductor substrate, said second diffusion layers sandwiching saidsecond gate electrodes; a first insulating film formed on said firstdiffusion layer; second insulating films formed on the side surfaces ofsaid second gate electrodes; first silicide films formed on said firstgate electrodes; second silicide films formed on said second gateelectrodes; and third silicide films formed on said second diffusionlayers.
 2. The semiconductor memory device according to claim 1, whereinthe thickness A of each of said first and second insulating films asformed satisfies the relationship X/2≦A<Y/2, where X represents saidfirst distance, and Y represents said second distance.
 3. Thesemiconductor memory device according to claim 1, wherein said seconddistance is 1.3 to 5.0 times as said first distance.
 4. Thesemiconductor memory device according to claim 1, wherein said firstgate electrodes and said second gate electrodes are arranged apart fromeach other by said second distance.
 5. The semiconductor memory deviceaccording to claim 1, wherein said first insulating film fills theclearance between said first gate electrodes.
 6. The semiconductormemory device according to claim 1, wherein said first and secondinsulating films are formed of the same material.
 7. The semiconductormemory device according to claim 1, wherein each of said first andsecond insulating films is formed of an oxide film.
 8. The semiconductormemory device according to claim 1, wherein each of said first andsecond insulating films is formed of a silicon oxide film, a TEOS film,an ozone TEOS film, an HTO film, an SOG film, a coating type oxide film,an SA-CVD film, a plasma CVD film, or a PSG film.
 9. The semiconductormemory device according to claim 1, wherein each of said first, secondand third silicide films is formed of a cobalt silicide film, a titaniumsilicide film or a nickel silicide film.
 10. The semiconductor memorydevice according to claim 1, wherein each of said first, second andthird silicide films is a salicide film.
 11. The semiconductor memorydevice according to claim 1, wherein said first gate electrodes are thefloating gate electrodes in the memory cell region of a NAND type flashmemory.
 12. The semiconductor memory device according to claim 1,wherein: each of said first gate electrodes includes: a first conductivelayer formed on said semiconductor substrate with a third insulatingfilm interposed therebetween; a fourth insulating film formed on saidfirst conductive layer; and a second conductive layer formed on saidfourth insulating film; and each of said second gate electrodesincludes: a third conductive layer formed on said semiconductorsubstrate with a fifth insulating film interposed therebetween; and afourth conductive layer formed on said third conductive layer.
 13. Thesemiconductor memory device according to claim 12, wherein said firstconductive layer and said third conductive layers are layers of the samelevel, and said second conductive layer and said fourth conductivelayers are layers of the same level.
 14. The semiconductor memory deviceaccording to claim 12, wherein said first conductive layer performs thefunction of a floating gate, and said second conductive layer performsthe function of a control gate.
 15. The semiconductor memory deviceaccording to claim 12, further comprising a sixth insulating film formedbetween said third and fourth conductive layers and provided with anopen portion allowing said third and fourth conductive layers to conductpartly with each other.
 16. The semiconductor memory device according toclaim 15, wherein said open portion is positioned in the center betweensaid third and fourth conductive layers.
 17. The semiconductor memorydevice according to claim 15, wherein a plurality of said open portionsare formed between said third and fourth conductive layers.
 18. Thesemiconductor memory device according to claim 1, further comprising: athird gate electrode arranged in the vicinity of said second gateelectrodes and differing from said second gate electrodes in theconductivity type; a fourth silicide film formed on said third gateelectrode; a seventh insulating film formed on the side surface of saidthird gate electrode; a third diffusion layer formed in saidsemiconductor substrate and surrounded said third gate electrode; and afifth silicide film formed on said third diffusion layer.
 19. Thesemiconductor memory device according to claim 18, wherein said secondgate electrodes and said third gate electrode are arranged apart fromeach other by said second distance.
 20. The semiconductor memory deviceaccording to claim 1, further comprising: a fourth gate electrodearranged in the vicinity of said first gate electrodes; a sixth silicidefilm formed on said fourth gate electrode; a fourth diffusion layerformed in said semiconductor substrate and surrounded said fourth gateelectrode; and an eighth insulating film formed on said fourth diffusionlayer.
 21. The semiconductor memory device according to claim 20,wherein said first gate electrodes and said fourth gate electrode arearranged apart from each other by said first distance.
 22. Thesemiconductor memory device according to claim 20, wherein said fourthgate electrode constitutes a gate electrode of a selecting transistor.23. A semiconductor memory device comprising: a gate electrode of afirst conductivity type, said gate electrode including a firstconductive layer of said first conductivity type formed on asemiconductor substrate and a second conductive layer of a secondconductivity type, said second conductive layer being formed on saidfirst conductive layer.
 24. A semiconductor memory device comprising: afirst gate electrode of a first conductivity type, said first gateelectrode including a first conductive layer of said first conductivitytype formed on a semiconductor substrate and a second conductive layerof a second conductivity type formed on said first conductive layer; anda second gate electrode of said second conductivity type, said secondgate electrode including a third conductive layer of said secondconductivity type formed on said semiconductor substrate and a fourthconductive layer of said second conductivity type formed on said thirdconductive layer.
 25. The semiconductor memory device according to claim24, further comprising a third gate electrode of said secondconductivity type, said third gate electrode including a fifthconductive layer of said second conductivity type formed on saidsemiconductor substrate, a third insulating film formed on said fifthconductive layer, and a sixth conductive layer of said secondconductivity type formed on said third insulating film, said third gateelectrode being formed in a memory cell region, and said first andsecond gate electrodes being formed in a peripheral circuit region. 26.The semiconductor memory device according to claim 24, furthercomprising: a first insulating film formed between said first and secondconductive layers and provided with a first open portion allowing saidfirst and second conductive layers to conduct with each other; and asecond insulating film formed between said third and fourth conductivelayers and provided with a second open portion allowing said third andfourth conductive layers to conduct with each other.
 27. Thesemiconductor memory device according to claim 26, wherein said firstopen portion is positioned in the center between said first and secondconductive layers, and said second open portion is positioned in thecenter between said third and fourth conductive layers.
 28. Thesemiconductor memory device according to claim 26, wherein a pluralityof said first open portions are formed between said first and secondconductive layers, and a plurality of said second open portions areformed between said third and fourth conductive layers.
 29. Thesemiconductor memory device according to claim 24, wherein each of saidfirst to fourth conductive layers has an impurity concentration notlower than 1×10¹⁸ cm⁻³.
 30. The semiconductor memory device according toclaim 24, further comprising an element separating region formed of anelement separating insulating film serving to separate the elementregions in said semiconductor substrate, said second conductive layerand said fourth conductive layer being formed contiguous to each otheron said element separating insulating film.
 31. The semiconductor memorydevice according to claim 24, wherein each of said first and thirdconductive layers is of a two-layer structure.
 32. The semiconductormemory device according to claim 25, wherein each of said first, thirdand fifth conductive layers is of a two-layer structure.
 33. Thesemiconductor memory device according to claim 24, wherein said firstconductivity type is P-type, and said second conductivity type isN-type.
 34. The semiconductor memory device according to claim 25,wherein said fifth conductive layer performs the function of a floatinggate, and said sixth conductive layer performs the function of a controlgate.
 35. A method of manufacturing a semiconductor memory deviceprovided with a memory cell region having first gate electrodes and aperipheral circuit region having said gate electrodes, comprising:forming on a semiconductor substrate said first gate electrodes arrangedapart from each other by a first distance and said second gateelectrodes arranged apart from each other by a second distance largerthan said first distance; forming a first diffusion layer in saidsemiconductor substrate to surround said first gate electrodes; forminga first insulating film on said first diffusion layer and the sidesurfaces of said second gate electrodes; forming a second diffusionlayer in said semiconductor substrate to surround said second gateelectrodes; and forming first, second and third silicide films on saidfirst gate electrodes, on said second gate electrodes and on said seconddiffusion layer, respectively.
 36. A method of manufacturing asemiconductor memory device comprising a memory cell region having firstgate electrodes formed of first and second conductive layers and aperipheral circuit region having second gate electrodes formed of thirdand fourth conductive layers, comprising: forming a first insulatingfilm on a semiconductor substrate; forming a first electrode materiallayer into which an impurity is not introduced on said first insulatingfilm; forming an element separating region in said first electrodematerial layer, said first insulating film, and said semiconductorsubstrate, said element separating region formed of an elementseparating insulating film; forming said first conductive layer byapplying ion implantation and annealing to said first electrode materiallayer in said memory cell region; forming a second insulating film onsaid first conductive layer; forming a second electrode material layeron said second insulating film and said first conductive material layer,said second electrode material layer being not introduced an impurity;selectively removing said first and second electrode material layers,said first conductive layer and said second insulating film to form apattern of said first gate electrodes arranged apart from each other bya first distance and a pattern of said second gate electrodes arrangedapart from each other by a second distance larger than said firstdistance; forming a fist diffusion layer in said semiconductor substrateto surround said first gate electrodes; forming a third insulating filmon said first diffusion layer and the side surfaces of said second gateelectrodes; applying ion implantation and annealing to form said secondconductive layer on said first conductive layer, to form third andfourth conductive layers, and to form a second diffusion layer in saidsemiconductor substrate; and forming first, second and third silicidefilms on said second conductive layer, on said fourth conductive layer,and on said second diffusion layer, respectively.
 37. The method ofmanufacturing a semiconductor memory device according to claim 36,wherein the thickness A of said third insulating film as formedsatisfies the relationship X/2≦A<Y/2, where X represents said firstdistance, and Y represents said second distance.
 38. The method ofmanufacturing a semiconductor memory device according to claim 36,wherein said second distance is 1.3 to 5.0 times as said first distance.39. The method of manufacturing a semiconductor memory device accordingto claim 36, wherein said third insulating film fills the clearancebetween said first gate electrodes.
 40. The method of manufacturing asemiconductor memory device according to claim 36, wherein said thirdinsulating film is an oxide film.
 41. The method of manufacturing asemiconductor memory device according to claim 36, wherein said thirdinsulating film is formed of a silicon oxide film, a TEOS film, an ozoneTEOS film, HTO film, an SOG film, a coating type oxide film, an SA-CVDfilm, a plasma CVD film or a PSG film.
 42. The method of manufacturing asemiconductor memory device according to claim 36, wherein each of saidfirst, second and third silicide films is formed of a cobalt silicidefilm, a titanium silicide film or a nickel silicide film.
 43. The methodof manufacturing a semiconductor memory device according to claim 36,wherein each of said first, second and third silicide films is asalicide film.
 44. The method of manufacturing a semiconductor memorydevice according to claim 36, wherein said first gate electrodes are thefloating gate electrodes in a memory cell region of a NAND type flashmemory.
 45. The method of manufacturing a semiconductor memory deviceaccording to claim 36, wherein said first conductive layer performs thefunction of a floating gate, and said second conductive layer performsthe function of a control gate.
 46. The method of manufacturing asemiconductor memory device according to claim 36, wherein the surfaceof said element separating insulating film is positioned lower than thesurface of said first electrode material layer by partly removing saidelement separating insulating film after formation of said elementseparating region.
 47. The method of manufacturing a semiconductormemory device according to claim 36, further comprising: forming afourth insulating film between said third and fourth conductive layers;and forming an open portion in said fourth insulating film.
 48. Themethod of manufacturing a semiconductor memory device according to claim47, wherein said open portion is positioned in the center between saidthird and fourth conductive layers.
 49. The method of manufacturing asemiconductor memory device according to claim 47, wherein a pluralityof said open portions are formed between said third and fourthconductive layers.
 50. The method of manufacturing a semiconductormemory device according to claim 36, wherein, where said first gateelectrodes and said second gate electrodes are of the same conductivitytype, said third conductive layer is formed simultaneously in formingsaid first conductive layer.
 51. The method of manufacturing asemiconductor memory device according to claim 36, wherein each of saidfirst conductive layer in said first gate electrodes and said thirdconductive layer in said second gate electrodes is formed by using anelectrode material into which an impurity is not introduced.
 52. Themethod of manufacturing a semiconductor memory device according to claim36, further comprising: forming a third gate electrode in the vicinityof said first gate electrodes; forming a third diffusion layer in saidsemiconductor substrate to surround said third gate electrode; forming afifth insulating film on said third diffusion layer; and forming afourth silicide film on said third gate electrode.
 53. The method ofmanufacturing a semiconductor memory device according to claim 52,wherein said first gate electrodes and said third gate electrode arearranged apart from each other by said first distance.
 54. The method ofmanufacturing a semiconductor memory device according to claim 52,wherein said third electrode are a gate electrode of a selectingtransistor.
 55. A method of manufacturing a semiconductor memory deviceincluding a first region having a first gate electrode of a firstconductivity type formed of first and second conductive layers and asecond region having a second gate electrode of a second conductivitytype formed of third and fourth conductive layers, comprising: forming afirst insulating film on a semiconductor substrate; forming a firstelectrode material layer on said first insulating film; forming anelement separating region in said first electrode material layer, saidfirst insulating film and said semiconductor substrate, said elementseparating region formed of an element separating insulating film;applying ion implantation and annealing to said first electrode materiallayer in said second region to form said third conductive layer of saidsecond conductivity type; applying ion implantation and annealing tosaid first electrode material layer in said first region to form saidfirst conductive layer of said first conductivity type; and forming asecond electrode material layer of said second conductivity type in saidfirst conductive layer, said third conductive layer and said elementseparating insulating film and forming said second conductive layer andsaid fourth conductive layer each formed of said second conductivematerial layer.
 56. The method of manufacturing a semiconductor memorydevice according to claim 55, wherein said first electrode materiallayer is formed of a first layer and a second layer, any one of saidfirst layer and second layer being a layer having an impurity of saidfirst conductivity type implanted thereinto and said impurity beingdiffused by annealing into the other layer to form said third conductivelayer.
 57. The method of manufacturing a semiconductor memory deviceaccording to claim 55, further comprising: forming said secondinsulating film to be positioned between said first and secondconductive layers and between said third and fourth conductive layers;and forming open portions in said second insulating film to permit saidfirst conductive layer to conduct with said second conductive layer andto permit said third conductive layer to conduct with said fourthconductive layer.
 58. The method of manufacturing a semiconductor memorydevice according to claim 57, wherein said open portions are formed inthe center between said first and second conductive layers and in thecenter between said third and fourth conductive layers.
 59. The methodof manufacturing a semiconductor memory device according to claim 57,wherein a plurality of said open portions are formed between said firstand second conductive layers and between said third and fourthconductive layers.
 60. The method of manufacturing a semiconductormemory device according to claim 55, wherein each of said first tofourth conductive layers has an impurity concentration not lower than1×10¹⁸ cm⁻³.
 61. The method of manufacturing a semiconductor memorydevice according to claim 55, wherein said second conductive layer andsaid fourth conductive layer are formed contiguous on said elementseparating insulating film.
 62. The method of manufacturing asemiconductor memory device according to claim 55, wherein said firstconductivity type is P-type and said second conductivity type is N-type.63. A method of manufacturing a semiconductor memory device providedwith a peripheral circuit region having a first region including a firstgate electrode of a first conductivity type formed of first and secondconductive layers and a second region including a second gate electrodeof a second conductivity type formed of third and fourth conductivelayers, and with a memory cell region having a third gate electrode ofsaid second conductivity type formed of fifth and sixth conductivelayers, comprising: forming a first insulating film on a semiconductorsubstrate; forming a first electrode material layer on said firstinsulating film; forming an element separating region in said firstelectrode layer, said first insulating film and said semiconductorsubstrate, said element separating region formed of an elementseparating insulating film; applying ion implantation and annealing tosaid first electrode material layer positioned in said second region andsaid memory cell region to form said third conductive layer and saidfifth conductive layer of said second conductivity type; applying ionimplantation and annealing to said first electrode material layer insaid first region to form said first conductive layer of said firstconductivity type; forming a second insulating film on said fifthconductive layer; and forming a second electrode material layer of saidsecond conductivity type in said second insulating film, said firstconductive layer, said third conductive layer and said elementseparating insulating film, followed by patterning said second electrodematerial layer to form said second conductive layer, said fourthconductive layer and said sixth conductive layer each formed of saidsecond electrode material layer.
 64. The method of manufacturing asemiconductor memory device according to claim 63, wherein said firstelectrode material layer is formed of a first layer and a second layer,any one of said first layer and second layer being a layer having animpurity of said first conductivity type implanted thereinto and saidimpurity being diffused by annealing into the other layer to form saidthird conductive layer and said fifth conductive layer.
 65. The methodof manufacturing a semiconductor memory device according to claim 63,further comprising: forming said second insulating film to be positionedbetween said first and second conductive layers and between said thirdand fourth conductive layers; and forming open portions in said secondinsulating film to permit said first conductive layer to conduct withsaid second conductive layer and to permit said third conductive layerto conduct with said fourth conductive layer.
 66. The method ofmanufacturing a semiconductor memory device according to claim 65,wherein said open portions are formed in the center between said firstand second conductive layers and in the center between said third andfourth conductive layers.
 67. The method of manufacturing asemiconductor memory device according to claim 65, wherein a pluralityof said open portions are formed between said first and secondconductive layers and between said third and fourth conductive layers.68. The method of manufacturing a semiconductor memory device accordingto claim 63, wherein each of said first to sixth conductive layers hasan impurity concentration not lower than 1×10¹⁸ cm⁻³.
 69. The method ofmanufacturing a semiconductor memory device according to claim 63,wherein said second conductive layer and said fourth conductive layerare formed contiguous on said element separating insulating film. 70.The method of manufacturing a semiconductor memory device according toclaim 63, wherein said first conductivity type is P-type and said secondconductivity type is N-type.
 71. The method of manufacturing asemiconductor memory device according to claim 63, wherein said fifthconductive layer performs the function of a floating gate and said sixthconductive layer performs the function of a control gate.